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MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE
The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2. The delay increment of the EP196 has a digitally selectable resolution of about 10 ps and a range of up to 10 ns. The required delay is selected by the 10 programmable data select inputs D[0:9] which are latched on chip by a high signal on the latch enable (LEN) control. Delays are set by programming values of 0000000000 to 1111111111 on the D0 (LSB) through D9 (MSB) as shown in Table 1. Because the EP196 is designed using a chain of multiplexers, it has a fixed minimum delay of 2.4 ns. An additional pin, D10, is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs. Select input pins, D0-D10, may be threshold controlled by combinations of interconnects between VEF (pin 7) and VCF (pin 8) for CMOS, ECL, or TTL level signals. TTL and CMOS operation is available in PECL mode only. For CMOS input levels, leave VCF and VEF open. For ECL operation, short VCF and VEF (pins 7 and 8). For TTL level operation, connect a 1.5 V supply reference to VCF and leave open VEF pin. The 1.5 V reference voltage to VCF pin can be accomplished by placing a 2.2 kW resistor between VCF and VEE for 3.3 V power supply. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation.
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MC100 EP196 LQFP-32 FA SUFFIX CASE 873A AWLYYWW 32 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
*For additional information, refer to Application Note AND8002/D
ORDERING INFORMATION
Device MC100EP196FA MC100EP196FAR2 Package LQFP-32 LQFP-32 Shipping 250 Units/Tray 2000/Tape & Reel
* Maximum Frequency > 1.2 GHz Typical * PECL Mode Operating Range: VCC = 3.0 V to 3.6 V * NECL Mode Operating Range: VCC = 0 V * * * * *
with VEE = -3.0 V to -3.6 V Open Input Default State Safety Clamp on Inputs A Logic High on the EN Pin Will Force Q to Logic Low D[0:10] Can Accept Either ECL, CMOS, or TTL Inputs VBB Output Reference Voltage with VEE = 0 V
(c) Semiconductor Components Industries, LLC, 2002
1
August, 2002 - Rev. 3
Publication Order Number: MC100EP196/D
MC100EP196
VEE D0 VCC Q Q VCC VCC FTUNE
PIN DESCRIPTION
PIN FUNCTION ECL Signal Input ECL Input Enable CMOS, ECL, or TTL Select Inputs ECL Signal Output ECL Latch Enable Input ECL Minimum Delay Set Input ECL Maximum Delay Set Input ECL Cascade Signal Output
24 D1 D2 D3 VEE D4 D5 D6 D7 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 EN CASCADE CASCADE VCC SETMAX SETMIN LEN
IN*, IN* EN* D[0:10]* Q, Q LEN* SETMIN* SETMAX* CASCADE, CASCADE VBB VEE VCC VEE VCF
MC100EP196
13 12 11 10 9
Output Reference Voltage Positive Supply Negative Supply CMOS, ECL, or TTL Input Select Input ECL Reference Mode Connection Fine Tuning Input
2
3
4
5
6
7
8
D8
D9 D10 IN
IN VBB VEF VCF
VEF FTUNE*
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
TRUTH TABLE EN EN LEN LEN SETMIN SETMIN SETMAX SETMAX VCF VCF VCF * ** L* H L* H L* H L* H VEF Pin** No Connect 1.5 V $100 mV
* Pins will default LOW (VEE) when left open. SETMIN will override SETMAX if both pins are high.
Q = IN Q Logic Low Pass Through D[0:10] Latch D[0:10] Normal Mode Min Delay Path Normal Mode Max Delay Path ECL Mode CMOS Mode TTL Mode***
Internal pulldown will provide logic low if pin left unconnected. Short VCF (pin 8) and VEF (pin 7).
*** For TTL Mode, if no external voltage can be provided, the reference voltage can be provided by connecting the appropriate resistor between VCF and VEE pins. Power Supply 3.3 V Resistor Value 5% (Tolerance) 2.2 kW
DATA INPUT OPERATING VOLTAGE TABLE POWER SUPPLY (VCC, VEE) PECL NECL DATA SELECT INPUTS (D [0:10]) CMOS n N/A TTL n N/A PECL n N/A NECL N/A n
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MC100EP196
Q Q
0
1
Table 1. Theoretical Delta Delay Values
(does not include fixed minimum delay) D10 D(9:0) Value 0000000000 Delay Value 0 ps 10 ps 20 ps 30 ps 40 ps 50 ps 60 ps 70 ps 80 ps 160 ps 320 ps 640 ps 1280 ps 2560 ps 5120 ps 10230 ps 10240 ps (SET MAX) Comment (SET MIN)
0
1
1024 GD*
512 1 GD*
0000000001
D9
0000000010 *GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE 0000000011 0000000100 0000000101 0000000110 (FIXED MINIMUM DELAY APPROX. 2.4 ns) 0000000111 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 1 XXXXXXXXXX
256 GD*
128 GD*
64 GD*
10 BIT LATCH
32 GD*
16 GD*
D4
0
1
D5
0
1
D6
0
1
D7
0
1
D8
0
1
Table 2. Typical FTUNE Delay Pin
Input Range VCC-VEE (V) Output Range 0 - 60 (ps)
8 GD*
D3
0
1
CASCADE
4 GD*
2 GD*
D1
0
1
Latch
CASCADE
D2
0
1
1 GD*
SET MAX
SET MIN
LEN
VBB
D0
0
1
Figure 2. Logic Diagram
VEE
VCF
VEF
EN
IN
IN
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D10
MC100EP196
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW N/A > 2 kV > 100 V > 2 kV Level 2 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 1279 Devices
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
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MC100EP196
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd < 2 to 3 sec @ 248C 32 LQFP 32 LQFP 32 LQFP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 80 55 12 to 17 265 Units V V V V mA mA mA C C C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIH Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) PECL CMOS TTL Input LOW Voltage (Single-Ended) PECL CMOS TTL Output Voltage Reference TTL Mode Input Detect Voltage @ IVCF = 700 mA Reference Voltage for ECL Mode Connection Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current IN, IN, D0-D10, EN Setmin, Setmax, LEN IIHH IIL IILL FTUNE Input Current @ VCC Input LOW Current FTUNE Input LOW Current @VEE IN IN -150 -150 -200 400 400 400 -150 -150 -200 400 400 400 -150 -150 -200 400 400 400 mA mA mA Min 100 2155 1355 2075 2000 2000 1355 0 0 1775 1.4 1850 2.0 1875 1.5 1979 Typ 125 2300 1520 Max 160 2405 1605 3300 3300 3300 1675 800 800 1975 1.6 2100 3.3 Min 110 2155 1355 2075 2000 2000 1355 0 0 1775 1.4 1800 2.0 1875 1.5 1975 25C Typ 130 2300 1500 Max 170 2405 1605 3300 3300 3300 1675 800 800 1975 1.6 2125 3.3 Min 110 2155 1355 2075 2000 2000 1355 0 0 1775 1.4 1800 2.0 1875 1.5 1966 85C Typ 135 2300 1485 Max 175 2405 1605 3300 3300 3300 mV 1675 800 800 1975 1.6 2125 3.3 mV V mV V mA Unit mA mV mV mV
VIL
VBB VCF VEF VIHCMR IIH
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V. 4. All loading with 50 W to VCC-2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100EP196
DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.0 V to -3.6 V (Note 6)
-40C Symbol IEE VOH VOL VIH VIL VBB VEF VIHCMR IIH Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) NECL Input LOW Voltage (Single-Ended) NECL Output Voltage Reference Mode Connection Input HIGH Voltage Common Mode Range (Differential) (Note 8) Input HIGH Current IN, IN, D0-D10, EN Setmin, Setmax, LEN FTUNE Input Current @ VCC Input LOW Current FTUNE Input LOW Current @ VEE IN IN -150 -150 -200 Min 100 -1145 -1945 -1225 -1945 -1525 -1450 Typ 125 -1000 -1780 -1394 -1417 -1425 -1321 Max 160 -895 -1695 -880 -1625 -1325 -1200 0 Min 110 -1145 -1945 -1225 -1945 -1525 -1500 25C Typ 130 -1000 -1800 -1412 -1435 -1425 -1325 Max 170 -895 -1695 -880 -1625 -1325 -1175 0 Min 110 -1145 -1945 -1225 -1945 -1525 -1500 85C Typ 135 -1000 -1815 -1429 -1453 -1425 -1334 Max 175 -895 -1695 -880 mV -1625 -1325 -1175 0 mV mV V mA 400 400 400 -150 -150 -200 400 400 400 -150 -150 -200 400 400 400 mA mA mA Unit mA mV mV mV
VEE+2.0
VEE+2.0
VEE+2.0
IIHH IIL IILL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. 7. All loading with 50 W to VCC-2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100EP196
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 9)
-40C Symbol fmax tPLH tPHL Characteristic Maximum Frequency Propagation Delay IN to Q; D(0-9) = 0 IN to Q; D(0-9) = 1023 EN to Q; D(0-9) = 0 D10 to CASCADE Programmable Range {D(0-9) = HI} - {D(0-9) = LO} Step Delay (Note 10) D0 High D1 High D2 High D3 High D4 High D5 High D6 High D7 High D8 High D9 High Mono tSKEW ts Monotonicity (Note 11) Duty Cycle Skew (Note 12) |tPHL-tPLH| Setup Time D to LEN D to IN (Note 13) EN to IN (Note 14) th Hold Time LEN to D IN to EN (Note 15) tR Release Time EN to IN (Note 16) SET MAX to LEN SET MIN to LEN tjit VPP tr tf Random Clock Jitter @ 1.2 GHz, SETMAX Delay Input Voltage Swing (Differential) Output Rise/Fall Time 20-80% (Q) 20-80% (CASCADE) 85 100 110 150 130 200 95 110 120 160 145 210 110 125 135 175 160 225 150 150 400 300 -105 70 165 3 800 1200 150 150 400 350 -120 110 180 3 800 1200 150 150 400 350 -140 160 205 3 800 1200 ps mV ps TBD 450 TBD 275 200 450 70 305 200 450 60 325 ps 150 100 150 -10 -130 -105 150 100 150 -70 -150 -120 150 100 150 -70 -165 -140 ps 12 28 46 64 137 293 590 1158 2317 4647 9 20 16 32 50 69 149 313 629 1237 2472 4955 10 22 11 39 63 154 337 681 1353 2712 5440 11 27 ps 1810 9500 1780 350 8600 Min Typ 1.2 2210 11496 2277 450 9285 2610 13500 2780 550 10000 1960 10000 1930 380 9200 Max Min 25C Typ 1.2 2360 12258 2430 477 9897 2760 14000 2930 580 10700 2180 10955 2150 420 9900 Max Min 85C Typ 1.2 2580 13454 2650 520 10875 2980 15955 3150 620 ps 12000 ps Max Unit GHz ps
tRANGE Dt
90 245 530 1060 2160 4335
185 335 650 1265 2490 5010
100 260 560 1130 2290 4590
200 370 710 1355 2680 5385
90 270 600 1200 2450 4935
225 410 770 1520 3015 6015 ps ps
9. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. 10. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range. 11. The monotonicity indicates the increased delay value for each binary count increment on the control inputs D(0-9). 12. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 13. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 14. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than VCC - 1425 mV to that IN/IN transition. 15. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than VCC - 1425 mV to that IN/IN transition. 16. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times.
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MC100EP196
Using the FTUNE Analog Input The analog FTUNE pin on the EP196 device is intended to add more delay in a tunable gate to enhance the 10 ps resolution capabilities of the fully digital EP196. The level of resolution obtained is dependent on the voltage applied to the FTUNE pin. To provide this further level of resolution, the FTUNE pin must be capable of adjusting the additional delay finer than the 10 ps digital resolution (See Logic Diagram). This requirement is easily achieved because a 60 ps additional delay can be obtained over the entire FTUNE voltage range (See Figure 3). This extra analog range ensures that the FTUNE pin will be capable even under worst case conditions of covering a digital resolution. Typically, the analog input will be driven by an external DAC to provide a digital control with very fine analog output steps. The final resolution of the device will be dependent on the width of the DAC chosen. To determine the voltage range necessary for the FTUNE input, Figure 3 should be used. There are numerous voltage ranges which can be used to cover a given delay range; users are given the flexibility to determine which one best fits their designs.
90 80 70 60 DELAY (ps) 50 40 30 20 10 0 -10 -3.3 -2.97 -2.64 -2.31 VEE -1.98 -1.65 -1.32 -0.99 FTUNE VOLTAGE (V) -0.66 -0.33 0 VCC 85C VCC = 0 V VEE = -3.3 V 25C -40C
Figure 3. Typical EP196 Delay versus FTUNE Voltage
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MC100EP196
Cascading Multiple EP196s To increase the programmable range of the EP196, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP196s without the need for any external gating. Furthermore, this capability requires only one more address line per added E196. Obviously, cascading multiple programmable delay chips will result in a larger programmable range; however, this increase is at the expense of a longer minimum delay.
Need if Chip #3 is used
Figure 4 illustrates the interconnect scheme for cascading two EP196s. As can be seen, this scheme can easily be expanded for larger EP196 chains. The D10 input of the EP196 is the cascade control pin. With the interconnect scheme of Figure 4 when D10 is asserted, it signals the need for a larger programmable range than is achievable with a single device. The A11 address can be added to generate a cascade output for the next EP196. For a 2-device configuration, A11 is not required.
ADDRESS BUS
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 D8 D9 D10
D6
D5
D4
VEE
D3
D2
D1 VEE D0
D7 D8 D9 D10
D6
D5
D4
VEE
D3
D2
D1 VEE D0
EP196
IN INPUT IN VBB VEF CASCADE CASCADE SETMAX SETMIN VCF LEN VEE
VCC Q
EP196
IN IN VBB VEF CASCADE SETMIN VCF LEN VEE CASCADE SETMAX
VCC Q OUTPUT
CHIP #2
Q VCC VCC FTUNE EN
CHIP #1
Q VCC VCC FTUNE EN
VCC
VCC
DAC Figure 4. Cascading Interconnect Architecture
An expansion of the latch section of the block diagram is pictured in Figure 5. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D10 of chip #1 in Figure 4 is low, the cascade output will also be low while the cascade bar output will be a logical high. In this condition, the SETMIN pin of chip #2 will be asserted and thus all of the latches of chip #2 will be reset and the device will be set at its minimum delay. Chip #1, on the other hand, will have both SETMIN and SETMAX deasserted so that its delay will be controlled entirely by the address bus A0-A9. If the delay needed is greater than can be achieved with 1023 gate delays (1111111111 on the A0-A9 address bus), D10 will be asserted to signal the need to cascade the delay to the next EP196 device. When D10 is asserted, the SETMIN pin of
chip #2 will be deasserted and the SETMAX pin asserted, resulting in the device delay to be the maximum delay. Figure 6 shows the delay time of two EP196 chips in cascade. To expand this cascading scheme to more devices, one simply needs to connect the D10 pin from the next chip to the address bus and CASCADE outputs to the next chip in the same manner as pictured in Figure 4. The only addition to the logic is the increase of one line to the address bus for cascade control of the second programmable delay chip. Furthermore, to fully utilize EP196, the FTUNE pin can be used for additional delay and for finer resolution than 10 ps. As shown in Figure 3, an analog voltage input from DAC can adjust the FTUNE pin with an extra 60 ps of delay for each chip.
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MC100EP196
TO SELECT MULTIPLEXERS
BIT 0 D0 Q0 LEN SET MIN SET MAX
Set Reset
BIT 1 D1 Q1 LEN
Set Reset
BIT 2 D2 Q2 LEN
Set Reset
BIT 3 D3 Q3 LEN
Set Reset
BIT 4 D4 Q4 LEN
Set Reset
BIT 5 D5 Q5 LEN
Set Reset
BIT 6 D6 Q6 LEN
Set Reset
BIT 7 D7 Q7 LEN
Set Reset
BIT 8 D8 Q8 LEN
Set Reset
BIT 9 D9 Q9 LEN
Set Reset
Figure 5. Expansion of the Latch Section of the EP196 Block Diagram
VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2 INPUT FOR CHIP #1 D10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 D7 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 D6 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 D5 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 D4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 D3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 D1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 D0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 Delay Value 0 ps 10 ps 20 ps 30 ps 40 ps 50 ps 60 ps 70 ps 80 ps 160 ps 320 ps 640 ps 1280 ps 2560 ps 5120 ps 10230 ps Total Delay Value 4400 ps 4410 ps 4420 ps 4430 ps 4440 ps 4450 ps 4460 ps 4470 ps 4480 ps 4560 ps 4720 ps 5040 ps 5680 ps 6960 ps 9520 ps 14630 ps
VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2 INPUT FOR CHIP #1 D10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 D7 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 D6 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 D5 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 D4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 D3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 D1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 D0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 Delay Value 10240 ps 10250 ps 10260 ps 10270 ps 10280 ps 10290 ps 10300 ps 10310 ps 10320 ps 10400 ps 10560 ps 10880 ps 11520 ps 12800 ps 15360 ps 20470 ps Total Delay Value 14640 ps 14650 ps 14660 ps 14670 ps 14680 ps 14690 ps 14700 ps 14710 ps 14720 ps 14800 ps 14960 ps 15280 ps 15920 ps 17200 ps 19760 ps 24870 ps
Figure 6. Cascaded Delay Value of Two EP196s
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MC100EP196
Multi-Channel Deskewing The most practical application for EP196 is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high-speed system. To deskew multiple signal channels, each channel can be sent through each EP196 as shown in Figure 7. One signal channel can be used as reference and the other EP196s can be used to adjust the delay to eliminate the timing skews. Nearly any high-speed system can be fine tuned (as small as 10 ps) to reduce the skew to extremely tight tolerances using the available FTUNE pin.
EP196 IN IN #1 Q Q
EP196 IN IN #2 Q Q
EP196 IN IN #N Control Logic Digital Data DAC Q Q
Figure 7. Multiple Channel Deskewing Diagram
Q Driver Device Q 50 W 50 W
D Receiver Device D
VTT VTT = VCC - 2.0 V
Figure 8. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
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MC100EP196
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AND8002 AND8009 AND8020 AND8066 AND8072 - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices Interfacing with ECLinPS Thermal Analysis and Reliability of WIRE BONDED ECL
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC100EP196
PACKAGE DIMENSIONS
LQFP FA SUFFIX 32-LEAD PLASTIC PACKAGE CASE 873A-02 ISSUE A
A
32 4X 25
A1
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
CE
SECTION AE-AE
X DETAIL AD
GAUGE PLANE
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0.250 (0.010)
H
W
K
Q_
-T-, -U-, -Z-
EE EE EE EE
MC100EP196
Notes
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MC100EP196
Notes
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MC100EP196
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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MC100EP196/D

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